1. Field of the Invention
This invention relates to interconnection between wiring in multilayer electrical and electronic devices and more particularly to via interconnections and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,716,218 of Farnsworth et al. for xe2x80x9cProcess for Manufacturing an Interconnect for Testing a Semiconductor Diexe2x80x9d shows a structure, and a process of manufacture of a compliant interconnect wherein a series of contacts are formed conformally over an undulating insulator layer with tapered side walls where the structure shape is optimized for the ability to connect to another electrical component.
U.S. Pat. No. 5,861,344 of Roberts et al. for xe2x80x9cFacet Edge for Improved Step Coverage of Integrated Circuit Contactsxe2x80x9d describes a structure and a method for providing a facet etch to improve step coverage where two conductive layers converge at and in a via hole; and over at least one layer of insulation to improve the structural integrity of a via having a fixed geometry. The contact area, and thus the maximum potential electrical performance are not increased.
U.S. Pat. No. 5,998,295 of Madurawe for xe2x80x9cMethod of Forming a Rough Region on a Substratexe2x80x9d describes a method of forming a rough region over a substrate, where a metal line converges into a contact over at least one layer of insulation. Methods are described for creating variations in topology of a semiconductor surface for the sole purpose of achieving optical reference points on an otherwise flat surface to enable visual alignment for process tooling. The patent does not relate to any electrical properties of the semiconductor.
U.S. Pat. No. 6,013,547 of Liaw for xe2x80x9cProcess for Creating a Butt Contact Opening for a Self-Aligned Contact Structurexe2x80x9d describes a method of forming a metal connection (via a butt contact opening) between a gate structure and active semiconductor devices. The process of Liaw is employed primarily for manufacturing MOSFET SRAM (N type and P type) devices. After the devices and gates are constructed a step of etching by RIE with methyl trifluoride gas (CHF3) is used to remove silicon oxide capping the gate structures to make openings for connection to the gates of FET devices. There is a process problem that the invention addresses, which is the undesired removal, during the silicon oxide RIE step, of portions of lightly doped source and drain regions in addition to removal of areas of device isolation insulators. The Liaw patent teaches applying an organic layer, polyimides or BARC (bottom anti-reflective coatings), over the layer before RIE etching the butt contact opening. The organic layer then protects the source and drain regions as well as the insulator areas during RIE of the silicon oxide. The organic and silicon oxide are removed at different rates in RIE, in addition various RIE chemistries can be used to control removal rates. The Liaw patent describes a method of protecting areas of the structure from removal during connection formation, but it does not describe a way to increase the bottom contact area. No patterning is done to layers below the layer being processed to enhance connection area, which one of the key features of the present invention. The Liaw patent describes a sequence of process steps that may be used on the layer being processed to control the area where material is removed. In summary, the Liaw patent describes a way to limit the regions where material is removed during device connection formation.
U.S. Pat. No. 5,834,365 of Ming-Tsung Liu et al. for a xe2x80x9cMethod of Forming a Bonding Padxe2x80x9d describes method of bonding, where, a plurality of metal layers converge over an undulating insulator layer and forms an additional bond area (pad) by creating metal features on the layer below. These features replicate up into the bond pad. The features used to increase bond area use real estate that could otherwise be used for active features. This technique would potentially reduce wireability. The Liu et al. patent builds features with some photolithography and metallization steps, to get features on a fine enough scale to affect the via areas we have would require semiconductor manufacturing processes. Features that fine would be totally planarized by polyimide insulators as thick as are used in Thin Film (TF) packaging. It appears that the bonding pad described applies to features in the 100""s of microns, but does not apply to features in the 10""s of microns. It probably cannot be used in internal wiring levels, there may not be xe2x80x9cfreexe2x80x9d space to build the topography enhancement features in internal wiring levels.
See U.S. Pat. No. 5,494,853 of Lur for xe2x80x9cMethod to Solve Holes in Passivation by Metal Layoutxe2x80x9d and U.S. Pat. No. 5,956,615 of Nguyen et al. for xe2x80x9cMethod of Forming a Metal Contact to Landing Pad Structure in an Integrated Circuit.xe2x80x9d
FIGS. 1A-1C are cross-sectional views of sequence of steps in the manufacture of a device 10 which illustrate a Prior Art method of forming a thin film via 27 (FIG. 1C) through a polyimide layer 24 which provides interconnection between a top conductor line 28 above an upper polyimide layer 24 and another conductor line 17 below the polyimide layer 24.
In FIG. 1A, a Prior Art device 10 is shown in an intermediate stage of fabrication. Device 10 is formed on a planar substrate 12 composed of a non-conductive material such as undoped silicon semiconductor material or a dielectric material. Initially, a first conductor line 14, which comprises a thin metal film is formed on the planar surface of the substrate 12. Then a planar, first polyimide layer 16 was formed covering the first conductor line 14 as well as the exposed surface of the substrate 12. However, subsequent to formation of planar, first polyimide layer 16, a via hole 15 therethrough was filled with the metallization of a via 18 which was formed through the first polyimide layer 16. The via hole 15 reached down to expose a portion of the conductor line 14. Then, an intermediate, second, conductor line 17 was formed on the surface of the planarized, first polyimide layer 16 reaching down into the via hole 15 to form the via 18 with the intermediate, second, conductor line 17 in electrical and mechanical contact with first conductor line 14. As will be well understood by those skilled in the art, a widened area of the line segment 17, often referred to as a landing pad 19 is formed in a line segment where a second via 27 is to be formed. As shown the line 17 and the metal landing pad 19 are planar and are formed on the flat planar surface of the polyimide layer 16 so that from the cross-sectional view in FIGS. 1B and 1C no recognizable difference its configuration or thickness can be discerned. Then a planarized, second polyimide layer 24 was formed covering the intermediate, second, conductor line 17 and the exposed surface of the first polyimide layer 16.
In FIG. 1B, the device of FIG. 1A is shown after a via hole 26 with sidewalls 26W has been formed through the second polyimide layer 24 exposing a portion of the surface of the intermediate, second, conductor line 17, which comprises a thin metal film. The via hole 26 with sidewalls 26W has been formed by ablation with an excimer laser beam 29 passing through opening 25xe2x80x2 in a laser mask 25 which blocks the laser beam 29 from reaching other portions of the device 10. The etching of the second polyimide layer 24 by the laser beam 29 was stopped at the time at which the top surface of conductor line 17 was exposed. The via 26 hole and via 27 may be formed at the terminating end of line 17.
In FIG. 1C, the device 10 of FIG. 1B is shown after a third conductor line 28 was formed on the surface of the planarized, second polyimide layer 24 reaching down to form a second via 27 with sidewalls 27W over the sidewalls 26W of the via hole 26. The third conductor line 28 is in electrical and mechanical contact with the intermediate, second, conductor line 17. The location of an ablated hole 26 in which the via 27 is formed is located over the widened area of the line segment 17 comprising the landing pad 19.
While the Liaw patent, above, describes a method of protecting areas of the structure from removal during connection formation, it does not describe a way to increase bottom contact area as does the present invention. No patterning is done to layers below the layer being processed to enhance connection area, which one of the key features of the present invention. Unlike Liaw, the present invention describes a way to increase via connection area, without increasing via diameters or loosening ground rules.
The contact area, and the maximum potential electrical performance is increased by the present invention which increases the via contact area, providing a robust connection with increased contact area and thus enhanced electrical properties.
The present invention creates additional via area by ablating the polyimide under the via, without affecting features sizes, ground rules or free active area.
Current landing pads for thin film vias are flat. Increasing via contact area will result in a more reliable connection modifications to existing via ablation (widening the ablation) will increase via contact at the expense of capture criteria
In accordance with this invention, partially ablate the polyimide at subsequent via locations using the next via mask at the same level as the current vias are created masks are already available little added cycle time. Modifications to current ablation criteria fill the landing zone, without sacrificing the capture criteria with. That modification is required to account for deeper penetration depth due to the recess.
Further in accordance with this invention, a method of fabricating a via connection between two conductor lines formed above and below an insulating material comprises the following steps.
Form a recess in a top surface of a lower layer which is electrically relatively non-conductive or dielectric.
Form a first conductor line on the top surface of the lower layer reaching over at least a portion of the recess.
Form an upper layer composed of a dielectric material over the top surface of the lower layer and covering the first conductor line at least within the proximity of the recess.
Form a via hole reaching down toward the recess exposing the surface of the conductor line above the recess.
Form an intermediate, second, conductor line reaching down into the via hole into contact with the first conductor line above the recess.
Preferably, the lower layer and the upper layer comprise polymeric materials such as polyimide; the recess and the via are both formed by laser ablation of the lower layer and the same laser mask is employed for forming the recess and for forming the via; the recess has tapered walls and has a bottom within the lower layer; the via hole is formed by laser ablation of a hole through the upper layer having tapered walls and having a bottom exposing the intermediate, second, conductor line; the lower layer and the upper layer consist of polyimide material having a thickness of from about 7-10 micrometers.
Preferably, the laser ablation of the via hole is performed with a xenon/chlorine excimer laser in accordance with the parameters as follows:
and the laser ablation of the recess is performed with a xenon/chlorine excimer laser in accordance with the parameters as follows: